The present invention generally relates to a method of fabricating a semiconductor structures, and particularly to a method of forming a multi-chip stacked semiconductor structure including a thin interposer chip having a face-to-back bonding with another chip.
Recent development in three-dimensional (3D) chip stacking technology employs thin semiconductor chips to enable vertical stacking of multiple semiconductor chips. One of the difficulties in the 3D chip stacking technology stems from the thickness of semiconductor substrates employed in manufacturing a semiconductor chip. A typical semiconductor substrate as manufactured in a normal semiconductor processing sequence has a thickness from about 500 μm to about 1,000 μm. Formation of through-wafer vias (TWVs) that extend through the entirety of the thickness of the semiconductor substrate requires extraordinary processing sequences and high processing cost.
An alternative is to thin a semiconductor substrate after the formation of semiconductor devices and interconnects on a semiconductor substrate is completed and prior to dicing the semiconductor into semiconductor chips, or “dies.” By thinning the semiconductor substrate to a thickness less than 300 μm, through-wafer vias (TWVs) having a less height than the full thickness of the semiconductor substrate employed during a semiconductor manufacturing sequence may be employed to enable electrical connection between multiple semiconductor chips. In addition, thinned semiconductor substrate provides additional advantages such as improved thermal dissipation and improved device coupling across semiconductor devices located in different semiconductor chips that are vertically stacked.
The thinning of semiconductor chips is limited by the capability for handling the thinned semiconductor chips. This is because extremely thin semiconductor substrates or semiconductor chips having a thickness less than 200 microns are prone to breakage. Semiconductor chips having a thickness less than 100 microns are too fragile to handle with normal mechanical handling equipment without suffering from significant yield loss due to breakage.
Nonetheless, thin semiconductor chips having a thickness less than 100 microns offer a significant advantage to performance by reducing both the resistance and the capacitance of through-substrate vias (TSVs). Further, the reduction in the length of TSVs in a semiconductor chip enhances electromigration resistance of the TSVs because the shorter TSVs are less prone to electromigration. Thus, despite the difficulty in handling, thinned semiconductor chips are advantageous for high performance in multi-chip stacked semiconductor structures.